The present invention relates to a pipe-line type information processing apparatus and in particular to a system, in which, when operand data of a certain instruction is read out in a buffer memory control device having a buffer address array and a buffer memory, it is detected whether the operand data to be read out should be rewritten by a preceding instruction or not.
In a pipe-line type information processing apparatus, it is possible to increase instruction processing capacity by reading-out operand data of succeeding instructions without waiting for the termination of the execution of a certain instruction. However, in such an information processing apparatus, when operand data is read out by the execution of a certain instruction, it is necessary to detect that the read-out operand data is to be rewritten in memory by the preceding instruction whose execution is not yet terminated. This detection is called OSC (Operand Store Compare). The detection of the OSC can be effected by comparing the first address and the last address of the write-in, operand data of the preceding instruction effecting the write-in with the first address and the last address of the read-out operand data of the succeeding instruction, respectively.
Hereinbelow, in an information processing device using the virtual memory method, an architecture is dealt with, in which a plurality of virtual addresses correspond to one real address and the OSC should be judged in the real address space.
Heretofore, in an information processing apparatus based on the architecture stated above, the OSC judgment was effected on address bits, which are not transformed, in the case where the virtual address is transformed into a real address, among all the bit addresses of the virtual address. For example, supposing that a virtual address consists of 31 bits, in the case where the less significant 12 bits (bits 20 to 31) are address bits, which are not subjected to the address transformation, and the more significant 19 bits (bits 1 to 19) are address bits, which are subjected thereto, the virtual address and the corresponding real address are identical in the bits 20 to 31 and different in general in the bits 1 to 19. In this case, heretofore, when the address of the read-out operand data is compared with the address of the write-in operand data, the OSC detection was effected on the bits 20 to 31 in the two virtual addresses, which are to be compared.
As a publication relating to the OSC detection e.g. JP-A-57-200982 can be cited.
By the prior art technique described above, since the OSC detection is effected by comparing a part of the virtual addresses, although the detection speed is raised, this means that the OSC is detected excessively. That is, useless OSC detection outputs are issued in addition to the correct OSC detection outputs. Now, when an OSC is detected, the memory read-out of the succeeding reading-out instruction is obliged to be wait for that the preceding writing-in instruction is executed and written in the memory. If the OSC is detected excessively, the succeeding instruction can be obliged to wait uselessly, which decreases the instruction processing efficiency.
Further, when the OSC is detected, in order to eliminate the delay of the operand data reading-out operation by the succeeding instruction, the read-out data can be obtained by replacing the part changed by the write-in in the data read-out from the memory by the write-in data (JP-A-57-200982), which causes erroneous operation by an excessive OSC detection.
Although the excessive OSC detection can be prevented by comparing all the bits of the real addresses after the address transformation is completed, this enlarges the scale of the hardware constituting the comparing circuit. For example, when a virtual address is constituted by 31 bits, by the prior art technique stated above it is sufficient to compare 12 bits of 20 to 30 in the virtual address. On the contrary, by the real address after the address transformation, all the 31 bits of 1 to 31 constituting the real addresses are compared and therefore the scale of the hardware constituting the comparing circuit is increased by a factor of about 2.5 with respect to that required by the prior art technique described above.